1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular, to a semiconductor storage device with an error correction function.
2. Description of the Related Art
Ferroelectric memories (FeRAMs) are semiconductor storage devices that allow non-volatile storage of data based on two different magnitudes of polarization in a ferroelectric substance, using hysteresis characteristics of ferroelectric capacitors.
Generally, conventional ferroelectric memories have memory cells that employ architecture similar to that used in DRAM, wherein paraelectric capacitors are replaced with ferroelectric capacitors and the ferroelectric capacitors are connected to selection transistors in series (see, for example, Japanese Patent Laid-Open No. 2001-250376). Such memory cells are arranged in a grid pattern to constitute a memory cell array. When reading data, for example, a word line (selection line) corresponding to one of the memory cells to be read is driven in such a way that the corresponding selection transistor becomes conductive, by which the memory cell is connected to the corresponding bit line.
In addition, a so-called TC parallel unit serial connection type ferroelectric memory is known that is provided with memory cell blocks having memory cells connected in series, each of which memory cells is configured by parallel connection of a selection transistor and a ferroelectric memory (see, for example, Japanese Patent Laid-Open No. 2005-4811). For the TC parallel unit serial connection type ferroelectric memory, each of the memory cell blocks may be connected to a respective bit line when a block selection transistor with a block selection line (selection line) connected to its gate becomes conductive.
Whether a structure similar to that used in DRAM or a structure of TC parallel unit serial connection type, the ferroelectric memories may use the following schemes: “two transistors-two cells” (2T2C) scheme that uses two memory cells to read complementary data, and “one transistor-one cell” (1T1C) scheme that uses one memory cell to read complementary data.
By way of example, provided that a structure similar to DRAM is used, in the 2T2C scheme, a word line corresponding to one of the memory cells to be read and another word line corresponding to the complementary memory cell in which the complementary data is retained are selected to connect the memory cell to the bit line and the complementary memory cell to a complementary bit line. Then, plate voltage is applied to a plate line and voltage is applied across ferroelectric capacitors that configure the memory cell and the complementary memory cell, respectively. Charges from one ferroelectric capacitor in the memory cell are read to the bit line, while those from the other ferroelectric capacitor in the complementary memory cell are read to the complementary bit line, Then, the potentials of the pair of bit lines are compared and amplified by a sense amplifier.
On the other hand, in the 1T1C scheme, a word line connected to one of the memory cells to be read is selected to connect the memory cell to a corresponding bit line. Thereafter, plate voltage is applied to a plate line connected to the memory cell and voltage is applied across a ferroelectric capacitor that configures the memory cell. As a result, while charges from the ferroelectric capacitor are read to the bit line, a reference potential is applied to complementary bit lines, which constitute a pair of bit lines, by a reference potential generation circuit. The potentials of the pair of bit lines are compared and amplified by a sense amplifier. For the TC parallel unit serial connection type, it has a similar configuration to the other two schemes, except that a memory cell block is selected by a block selection transistor and a memory cell is selected by a word line.
The read operation of ferroelectric memory is destructive read because data is read by applying voltage across a ferroelectric capacitor to cause polarization inversion. Accordingly, after a read operation, it is necessary to write the read data back to the corresponding memory cell. In the conventional ferroelectric memories, for example, write back of “0” data may be performed by maintaining potentials of a pair of bit lines amplified by a sense amplifier circuit, and then write back of “1” data may be performed by reducing the potential of the plate line to a ground potential while maintaining the amplified potentials of the pair of bit lines.
Meanwhile, the ferroelectric memories may also be provided with error correction circuits (ECC circuits) for correcting data errors in a memory cell (see, for example, Japanese Patent Laid-Open No. 2002-175697). When ECC circuits are provided and error detection and correction is executed, it is necessary to maintain potentials of plate lines and bit lines during execution. Consequently, it will take longer to write “0” data than to write “1” data, causing so-called “imprint” (providing shifts in hysteresis characteristics of a corresponding ferroelectric capacitor), which could lead to degraded data reliability.